module add_cell
(
	input wire sys_clk,
	input wire sys_rst_n,

	input wire [15:0] oprand0,
	input wire [15:0] oprand1,
	input wire [15:0] oprand2,

	inout wire [15:0] ctrl_sig_inner,
	inout wire [15:0] addr_sig_inner,
	inout wire [15:0] data_sig_inner,

	inout wire work_ok_inner
);

reg cal_time;
reg cal_time_d1;

reg [15:0] res;
reg work_ok_represent;
reg [15:0] data_sig_represent;

assign work_ok_inner = work_ok_represent;
assign data_sig_inner = data_sig_represent;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		res <= 1'b0;
	else if ((ctrl_sig_inner[4] == 1'b1) && (addr_sig_inner == 6'd0))
		res <= oprand1 + oprand0;
	else
		res <= res;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		cal_time <= 1'b0;
	else if ((ctrl_sig_inner[4] == 1'b1) && (addr_sig_inner == 6'd0))
		cal_time <= 1'b1;
	else
		cal_time <= 1'b0;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		cal_time_d1 <= 1'b0;
	else
		cal_time_d1 <= cal_time;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		data_sig_represent <= 16'hz;
	else if (cal_time == 1'b1)
		data_sig_represent <= 16'h0;
	else if (cal_time_d1 == 1'b1)
		data_sig_represent <= res;
	else
		data_sig_represent <= 16'hz;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		work_ok_represent <= 1'bz;
	else if (cal_time == 1'b1)
		work_ok_represent <= 1'b0;
	else if (cal_time_d1 == 1'b1)
		work_ok_represent <= 1'b1;
	else
		work_ok_represent <= 1'bz;

endmodule